Clock data recovery and synchronization in interconnected devices

ABSTRACT

For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master&#39;s clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional Application of, under 35 U.S.C. §121,and claims priority to, under 35 U.S.C. §121, U.S. Non-Provisionalapplication Ser. No. 11/774,977, entitled Clock Recovery andSynchronization in Interconnected Devices, by John Yin, filed on Jul. 9,2007.

BACKGROUND OF THE INVENTION

This invention relates to computationally efficient clock data recoveryand synchronization in systems with interconnected devices having highrates of data transfer between devices.

Several trends in system design are increasing the demand for datatransfer in interconnected devices. The volume of data requiringtransfer between digital devices are constantly increasing, driving arequirement for higher data transfer rates. As an example, more digitalsignal processing applications are being performed by field programmablegate arrays (FPGAs) instead of conventional digital signal processors.System designs require more interconnections between FPGA devices andbetween FPGA devices and other devices. In the past, interfacearchitectures among multiple devices have typically used parallelconnections. The major drawback of parallel connections among multipleprocessing devices is a proliferation of input/output (I/O) pins. Toavoid this, the trend in current designs is to use high speed seriallinks. Currently, device connections within a system are migrating fromparallel backplanes to serial links.

Digital devices inherently require a clock for timing internal andexternal operations. For serial links, synchronization of the clocks atthe transmitting device and the receiving device is critical forsuccessful data transfer. A loss of synchronization may jeopardize theintegrity of the data. The clock provides the time base used to controlthe transfer of digital information. Reliable link design for two chipson a board include source synchronous design, where the transmittingdevice, or source, provides the data and a clock signal. The receivingdevice then synchronizes to the received clock signal. For communicationbetween boards, there is a need to minimize the number of wires, so aseparate clock signal on a separate wire is not used. Instead, thetransmitting device embeds the clock signal in the data. The receivingdevice recovers the clock signal embedded in the received signal.

Recovering the clock signal is referred to as clock data recovery (CDR)or clock recovery. CDR is required for two basic purposes: first, toestablish a timing signal to sample the incoming pulses or signal andsecond, to transmit outgoing pulses or signal at the same rate as thatof the incoming signal. A CDR module includes a phase lock loop (PLL).The PLL locks to the frequency and phase of an input signal andgenerates an output signal that is synchronized to the input signal.This output signal can be used as a clock signal. For this discussion,“clock” and “clock signal” both refer to a timing signal. Also for thisdiscussion, a “clock source” generates a clock signal that isindependent of any other clock signal in the system.

A system that includes an analog to digital converter (ADC) connected toa digital processor is a preferred implementation for many applications.Typically, an ADC is on the same board as the digital processor. This isa disadvantage for some applications. For example, in a digital radiosystem, transferring the received analog signal from an antenna oranalog front end (AFE) to the ADC requires expensive cables for radiofrequency (RF) signals. Positioning the ADC near the AFE improves signalreception and would allow the received analog signal to be digitized andtransmitted the over a lower cost digital link. However, the digitalsignal processing portion would require a computationally expensive CDRmodule for the digital link. It would be advantageous to avoid consumingthe resources of the digital signal processing portion of the systemwith CDR operations. For applications that transfer data between aremote ADC and a digital signal processing device, efficient clockrecovery would conserve system resources.

Clock data recovery is an important component of communication systemsand data networks. There are two major strategies for clocksynchronization, one used in telecommunication systems, described hereinas the telecom model, and the other used in data networks, describedherein as the datacom model. Both models include CDR modules forsynchronization on both sides of the communications link.

In the telecom model, a typical arrangement for a communication systemincludes a master station and one or more slave stations, each stationincluding a transmitter (TX) and a receiver (RX). The master station andthe slave station each include a CDR module for the received signal. Themaster includes a clock source for its TX. The master transmits theclock signal from the clock source in addition to data embedded in thetransmitted signal. The slave station includes a CDR module tosynchronize to the received clock signal. The output of the CDR moduleis the recovered RX clock signal. The slave station uses the recoveredRX clock signal to synchronize its TX clock signal. The synchronized TXclock signal is used for timing the slave's transmit signal. At thispoint, the slave's RX clock frequency matches the TX clock frequency.However, when the master station receives the signal transmitted fromthe slave, the master still has to synchronize to the phase of thereceived data, even though the clock frequency is matched. The phaseoffset is due to propagation delay that is a function of connectionlength and other distortions. The telecom model is prevalent the digitaltelephone network and wide area network (WAN) architectures.

In the datacom model, such as in Ethernet networks, the TX and RX ofeach station have independent timing control. Each station includes aclock source that produces a clock signal that is embedded in thetransmitted signal. Each station also includes a CDR module that locksto the embedded clock signal of the signal received from the otherstation.

In current architectures using the telecom model or the datacom model, adigital device requires CDR for every communication channel with anyremote device. Each CDR module includes a computationally expensive PLL.For example, current commercially available FPGAs include variousnumbers of PLL resources, where low end devices having 0 to 2 PLLs andhigh end devices having 4 to 8 PLLs. In addition, not all FPGA PLLs havethe same capability. In specialized high end FPGAs, some of the PLLs arecapable of supporting CDR functionality. Other FPGA devices have PLLswith lesser functionality that do not support CDR operations. Forsystems with multiple interconnected devices, the cost and complexityfor communication among devices increases for every channel. Thisproduces scalability problems, where the overhead for communicationbecomes prohibitive. The implementation of a PLL on an FPGA isphysically large on the die. Therefore, the PLL is the most expensiveresource on the FPGA. There is a need to reduce the number of PLLsrequired for communication in systems having interconnected FPGAs andother devices. Reducing the requirements for PLLs conserves the mostprecious resource of the FPGA, thus reducing the cost and complexity ofthe system. Similarly, for device implementations using an applicationspecific integrated circuit (ASIC), digital signal processor,microcontroller or microprocessor, reducing the number PLLs conservesresources for other application tasks. The present invention addressesthis need and others as described below.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method and anapparatus for synchronizing interconnected devices in a system usingfewer system resources than conventional systems. For a system havingtwo devices, a master device and a slave device, connected by a datatransfer interface, or link, the master device includes a phasecomparator that measures a phase offset in a signal received from theslave device with respect to the master's clock signal. The masterincludes a control symbol generator that determines a control symbolbased on the phase offset. The master includes an encoder that encodesthe control symbol in a transmit signal for the slave. The slaveincludes a decoder that decodes the control symbol from the signalreceived from the master. The slave uses the control symbol to adjustthe phase shift of a signal to be transmitted to the master device. Thephase shift is adjusted to compensate for the phase offset that occursdue to propagation over the link to the master. When the phasecompensated signal is received at the master, its phase offset issmaller than the original phase offset. This procedure can be performediteratively until the phase offset is within a desired tolerance.

Another object of the invention is to make systems with interconnecteddevices more scalable by reducing the communications overhead. In asystem with a master device in communication with a plurality of slavedevices over a plurality of links, the master includes a phasecomparator, a control symbol generator and an encoder for each slavedevice. The master produces and transmits a corresponding control symbolto each slave device. Each slave device applies its correspondingcontrol symbol to adjust the phase shift of its transmit signal. Thetransmit signal of each slave is phase compensated prior to transmissionover the corresponding link to the master. Each resulting receivedsignal at the master has a reduced phase offset as described above.

Another object of the invention is to reduce the complexity of the slavedevice by performing the phase compensation at the master device. Themaster device includes a phase adjuster in addition to the phasecomparator. The phase adjuster applies a phase shift to a signalreceived from the slave to reduce the phase offset. Alternatively, thephase adjuster applies a phase shift to the its transmit signal. Theslave's PLL locks to the phase shift in the signal received from themaster. In response to the phase shifted clock signal generated by thePLL, the slave produces a phase compensated signal for transmission tothe master. When the phase compensated signal is received at the master,the resulting received signal will have a smaller phase offset than theprevious received signal.

Another object of the invention is to provide efficient implementationfor an analog to digital converter (ADC) application. The slave deviceincludes an ADC that produces digital signal samples from an inputanalog signal. The slave device encodes the signal samples to form atransmit signal for the master. The procedures described above willresult in a phase compensated signal at the master.

An advantage of the present invention is the reduced complexity in asystem of interconnected devices and lower communications overhead.Another advantage is that the accuracy of the synchronization is notsacrificed in order to achieve lower complexity. Another advantage isthat the lower complexity reduces system cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an example of an interconnected system that includes amaster device with serial links and to a slave device, in accordancewith the prior art.

FIG. 2 is a block diagram of a matched chip set where each chip andprovides an interface between the respective devices and the respectivelinks, in accordance with the prior art.

FIG. 3 is a block diagram of the telecom model for timing control, inaccordance with the prior art.

FIG. 4 is a block diagram of the datacom model for timing control, inaccordance with the prior art.

FIG. 5 is a block diagram of the basic structure of a PLL, in accordancewith the prior art.

FIG. 6 is a block diagram of a preferred embodiment for the telecommodel.

FIG. 7 is a block diagram of an alternative embodiment of the slavedevice that includes a jitter buffer.

FIG. 8 is a block diagram for an alternative embodiment for the masterthat applies data comparisons instead of phase comparisons.

FIG. 9 shows a block diagram for an embodiment for the datacom model.

FIG. 10 illustrates examples of measuring phase offset and determining acontrol symbol, in accordance with the embodiments of FIG. 6 and FIG. 9.

FIG. 11 is a block diagram of an embodiment including a master device incommunication with multiple slave devices.

FIG. 12 is a block diagram of a preferred embodiment where the masteradjusts its received signal to compensate for phase offset.

FIG. 13 illustrates examples of signals corresponding to operation ofthe embodiment of FIG. 12.

FIG. 14 is a block diagram of a master linked with multiple slavedevices corresponding to the embodiment of FIG. 12.

FIG. 15 is a block diagram of a preferred embodiment where the masteradjusts its transmit signal to compensate for phase offset in itsreceived signal.

FIG. 16 illustrates an example of a signal corresponding to operation ofthe embodiment of FIG. 15.

FIG. 17 is a block diagram of a master linked to multiple slavescorresponding to the embodiment of FIG. 15.

FIG. 18 is a block diagram of an alternative embodiment for the slavedevice in FIGS. 12 and 15.

DETAILED DESCRIPTION

In any interconnected system, data transfer between devices requires thereceiving device to synchronize to signals received from thetransmitting device. FIG. 1 shows an example of an interconnected systemthat includes a master device 104 with serial links 101 and 102 to aslave device 100. The master device 104 and the slave device 100 eachinclude a CDR module, 108 and 106, respectively, to recover the clockfrom the their respective received signals. As described above in theBackground section, the PLL required for conventional CDR can consume aprohibitive amount of resources. Current solutions for this situationinclude commercially available matched chip sets. FIG. 2 shows a blockdiagram of a matched chip set where each chip, 206 and 208, provides aninterface between the respective devices 200 and 204 and the respectivelinks, 202 and 210. The matched chips 206 and 208 perform the CDRfunctions, including the PLL, and provide the recovered clocks 212 and214 and the received signals 216 and 218 to their respective devices,thus conserving the resources of the devices 200 and 204 themselves.

FIG. 3 is a block diagram of the telecom model for timing control. Themaster device 300 includes a clock source 302 for generating a clocksignal 305 for the TX 304. The clock signal 305 is embedded in thesignal to be transmitted along with the TX data 307. The transmit signalis transferred over a link 306 to the RX 308 of the slave device 310.The CDR module 312 in the slave device 310 applies a PLL to lock to thefrequency and phase of the received signal 309. The CDR module 312provides a clock signal 314 to the slave device's TX 316. The clocksignal 314 is embedded along with data 315 in the signal to betransmitted by the TX 316. The master's RX 320 receives the slave'stransmitted signal from link 318. At this point, the master's clocksource 302 and the slave's TX clock, and consequently the embedded clocksignal in the received signal 321, have matched frequencies. Ideally,the frequencies are the same. In reality, any frequency difference iswithin an acceptable tolerance. However, the phase of the master clocksignal 305 is offset with respect to the received signal 321 because ofpropagation effects. The master requires a CDR module 322 that includesa PLL to lock to the phase of the received signal.

FIG. 4 is a block diagram of the datacom model for timing control. Thefirst device 400 and the second device 410 communicate via links 406 and418. Each device 400 and 410 includes a clock source 402 and 414,respectively, and a CDR module, 422 and 412, respectively. Each device400 and 410 embeds its clock signal 405 and 415, respectively, in thesignal to be transmitted. Each CDR module 422 and 412 locks to thefrequency and phase of its received signal 421 and 409, respectively.There are no means for synchronizing the clocks of the two devices, soin addition to phase offset, the frequencies of the clocks can beslightly different. Normally the accuracy of the clock frequency isspecified as part of an industry standard for the devices in thenetwork. Typical frequency tolerance levels are 50 to 100 ppm. Thejitter buffers 430 and 434 store the respective received signals 421 and409 and compensate for frequency and phase differences.

Each device in the systems represented in FIGS. 1 through 4 requires aCDR module that includes a PLL. The structures and techniques for PLLsare well known in the art. The basic structure of a PLL is shown in FIG.5. The phase comparator 500 measures the phase offset, or skew, in thereceived signal 502 by comparing it to the phase of a reference signal504 output from a controlled oscillator 512. The controlled oscillator512 is a voltage controlled oscillator (VCO) in an analog PLL or anumber controlled oscillator (NCO) in a digital PLL. The loop filter 506smoothes the phase error 508 to generate a control signal 510 for thecontrolled oscillator 512. Based on the control signal 510, thecontrolled oscillator 512 adjusts its oscillations to more closely matchthe frequency and phase of the input signal 502.

Embodiments of the present invention eliminate the need for one PLL inone of the two communicating devices shown in FIGS. 1, 3 and 4. In thearchitecture of FIG. 2, an embodiment of the present invention mayeliminate the need for one of the matched chips or greatly reduce itscomplexity.

FIG. 6 is a block diagram of a preferred embodiment for the telecommodel. The master device 600 includes a phase comparator 602 thatcompares the received signal 604 to the clock signal 606 to measure aphase offset, or skew. The control symbol generator 608 determines acontrol symbol based on the phase offset. Encoder 610 encodes thecontrol symbol so that it occupies available control channels of thetransmit data 625. The functions of encoder 610 can be included theencoding operations for control data and payload data that normallyoccur for preparing TX data 625 for transfer as a transmit signal. TheTX 624 transfers the transmit signal with the embedded control symbolvia link 612 to the slave device 614. The receiver 628 receives thetransmit signal to form the received signal 615. The decoder 630extracts the control symbol from the received signal 615 and inputs itto the control module 619. The functions of the decoder 630 can beincluded in the decoding operations that normally occur for extractingcontrol data and payload data from the received signal 615. The CDRmodule 616 produces an RX clock signal 617 as described for the previousexample of FIG. 3. The control module 619 adjusts the phase of the RXclock signal 617 according to the control symbol to form a phasecompensated TX clock signal 618. Using the phase compensated TX clocksignal 618, the TX 626 forms a phase compensated transmit signal for TXdata 632. The phase compensation mitigates the phase shifts in thetransmit signal that occur during propagation over the link 627. As aresult of the phase compensation by the slave, the master's receiver 620produces a received signal 604 that is synchronized in the phase andfrequency with the master's clock signal 606. The phase compensationprovides the same degree of accuracy as if there were a local CDR moduleat the master.

The control symbol represents the phase adjustment applied to theslave's transmit clock signal 618. The control symbol can represent oneor more phase adjustment parameters, including a phase correction value,a phase step size (granularity), a number of phase steps, a delayinterval corresponding to the phase correction, a polarity indicator andother representations.

The controller 619 applies the phase adjustment to the recovered clocksignal 617, output by the CDR module 616, to produce a phase shiftedclock signal, the TX clock signal 618, at its output. The RX clocksignal 617 results from the conventional clock recovery operation of thePLL in the CDR module 616. The TX clock signal 618 is a phase shiftedversion of the RX clock signal 617 resulting from the phase compensationin accordance with the control symbol. In an alternative embodiment forthe telecom model, the slave's CDR module 616 produces one clock signalin the slave device. Since the slave's CDR module 616 has matched thefrequency of the master clock source 622, the phase adjustment can beimplemented by delaying the slave's transmit signal by a time intervalthat compensates for the phase offset. FIG. 7 is a block diagram of analternative embodiment of the slave device 614 that includes a jitterbuffer 707. The clock signal 777 functions as both the RX clock and theTX clock. Upon receiving the decoded control symbol, the controller 717produces a time shift control parameter for the jitter buffer 707. Inthis embodiment, the phase adjustment is converted to a correspondingtime shift adjustment to produce the time shift control parameter.Alternatively, the corresponding time shift adjustment can be calculatedby the control symbol generator 608 in the master device 600 to producethe control symbol for transfer to the slave device 614.

FIG. 8 is a block diagram for an alternative embodiment for the master600 that applies data comparisons instead of phase comparisons. Themaster 600 transmits a training pattern 717 to the slave 614 during atraining period. The slave 614 receives the transmitted training patternand retransmits it to the master 600 in a loopback procedure. Loopbackprocedures are well known to those of ordinary skill in the art. Themaster's receiver 620 receives the loopback signal. The data decoder 727decodes the pattern from the received loopback signal 737. The datacomparator 711 determines the shift in the received pattern 747 relativeto the test pattern 717 using methods well known to those skilled in theart. The control symbol generator 608 produces a control symbol based onthe detected shift. The control symbol is then encoded and transmittedto the slave as described previously with respect to FIG. 6.

FIG. 9 shows a block diagram for a preferred embodiment for the datacommodel. In the conventional datacom model described above with respect toFIG. 4, the first device 400 and the second device 410 include the sameelements. In an embodiment for the present invention, the communicatingdevices in the datacom model have some different elements. Thecommunicating devices will now be referred to as a master device 800 anda slave device 814. The master device 800 includes a phase comparator802 that determines the phase offset, or skew, of the received signal804 with respect to the clock signal 807 using techniques well known tothose skilled in the art. The control symbol generator 808 produces acontrol symbol based on the phase offset. The encoder 810 encodes thecontrol symbol for portions of the transmit data 825 that are used forcontrol data. The functions of encoder 810 can be included in theencoding operations for control data and payload data that normallyoccur for preparing TX data 825 for transfer. The transmitter 824transmits the TX data 825 with the embedded control symbol via the link812 to the receiver 828 of the slave device 814. The slave device 814includes CDR module 822 to recover the RX clock signal 824 from thereceived signal 815. The decoder 830 decodes the control symbol from thereceived signal 815 and provides it to transmit jitter buffer controller838. The functions of the decoder 830 can be included in the decodingoperations that normally occur for extracting control data and payloaddata from the received signal 815. The slave device 814 also includes atransmit jitter buffer 832 that stores transmit data 817. The transmitjitter buffer controller 838 determines a shift control parameter basedon the decoded control symbol. The transmit jitter buffer 832 applies ashift adjustment according to the shift control parameter to produce aphase compensated transmit signal. The transmitter 840 transmits thephase compensated transmit signal over link 827 to the receiver 820 ofthe master 800. The phase shifts due to propagation effects aremitigated by the compensating phase adjustment provided by the slave 814prior to transmission. Because of the phase compensation, the receivedsignal 804 is synchronized with the TX clock signal 807. The accuracy ofthe synchronization is substantially the same as that of a local PLL ina CDR module at the master 800.

The embodiments of the telecom model of FIG. 6 and the datacom model ofFIG. 9 each include a phase comparator 602 and 802, respectively, and acontrol symbol generator 608 and 808, respectively. The phasecomparators 602 and 802 can apply techniques well known in the art forcalculating phase offset. FIG. 10 illustrates examples of measuringphase offset and determining a control symbol. In a preferredembodiment, the phase offset is calculated by comparing the 50% risetime of at least one pulse of the TX clock signal 606 or 807 to the 50%rise time of a pulse in the received signal 604 or 804. A preferredembodiment includes a predetermined phase step size that is known atboth the master and the slave. The control symbol generator produces acontrol symbol that instructs the slave to increment or decrement thephase by the phase step size. The phase compensation at the slaveproduces a positive phase step or a negative phase step. Referring toFIG. 10, Example A illustrates a received signal pulse 1004 whose 50%rise time is delayed compared to the clock pulse 1002 by an amount +d.The control symbol generator produces a control symbol based on thepolarity of the phase offset. In this case, the control symbolrepresents a decrement command. At the slave station, the decrementcommand causes a phase adjustment of (− step). In the telecom model ofFIG. 6, the (− step) is applied to the PLL in the CDR module 616. In thedatacom model of FIG. 9, the (− step) is applied by the transmit jitterbuffer controller 828 to the transmit jitter buffer 832. The phaseadjusted transmit signal results in a received signal 1012 that is morephase aligned with the master clock signal 1010. Example B illustrates areceived signal pulse 1008 whose 50% rise time is ahead of the clockpulse 1006 by an amount −e. In this case, the control symbol generatorproduces a control symbol for an increment command. At the slavestation, the increment command causes a phase adjustment of (+ step).The phase adjusted transmit signal results in a received signal 1016that is more phase aligned with the master clock signal 1014. The phaseadjustments can continue iteratively until phase alignment is achievedwithin an acceptable tolerance. The accuracy of phase alignment will bethe substantially the same as that of a conventional CDR module at themaster using the same adjustments by positive or negative steps. One ofordinary skill in the art will appreciate that alternative strategiescan be applied for phase offset measurement and phase adjustment.Alternatives include but are not limited to:

-   -   1) at the master, calculating the average of several phase        offsets and generating the control symbol based on the average        phase offset,    -   2) using variable step sizes for phase adjustments.

The master can transmit the control symbol using control channels of atransmit signal carrying valid data. Alternatively, the master cantransmit the control symbol in an idle signal. An idle signal istransmitted during an idle state or invalid state when payload data arenot transmitted. A preferred embodiment uses 8 B/10 B encoding known tothose skilled in the art and described in the book, “Ethernet theDefinitive Guide” by Charles E. Spurgeon, pages 166-7. An 8 B/10 Bencoder uses 10 bits to encode 8 bit data words. This maps 256 datawords, corresponding to 8 bits, to 1024 possible words. Some of the 768spare words are used for control words and others are not used. Theencoder 606 for the telecom model and the encoder 810 for the datacommodel can encode the control symbol using one or more of the sparewords. For embodiments using a training pattern, such as that depictedin FIG. 8, the master can embed the training pattern in an idle signalor in a portion of a transmit data frame reserved for control data.

FIG. 11 is a block diagram of an embodiment including a master device1100 in communication with multiple slave devices 1102 i. Each of theslave devices 1102 i includes a phase compensation block 1106 i thatuses an i^(th) control symbol to apply a phase shift in the transmitdata as described above with respect to FIGS. 6, 7 and 9. The masterdevice 1100 includes a phase control feedback processor 1104 i thatmeasures the phase offset in the i^(th) received signal from the i^(th)slave device, as described above with respect to FIGS. 6, 8 and 9. Thei^(th) phase control feedback processor 1104 i generates an i^(th)control symbol which is encoded for transmission to the i^(th) slavedevice. The phase control feedback processor 1104 i can replace the PLLthat would be required for each link in a conventional architecture.

In the embodiments described thus far, the phase feedback control looppasses from the master to the slave and the phase compensation isperformed at the slave. The phase control feedback ultimately results ina phase compensated receive signal at the master. These embodiments areadvantageous for conserving the resources of the master device. Removingthe computationally expensive PLL that would otherwise be required foreach link and replacing it with simpler phase comparison frees resourcesat the master device for other operations in the application.

In the embodiments described in the following with respect to FIGS. 12to 18, the phase feedback control loop including phase adjustment isperformed at the master. These embodiments are preferable when there areresources available for phase adjustment at the master and it isdesirable to conserve resources at the slave. These embodiments are moreefficient than conventional architectures because they do not include aPLL at the master.

FIG. 12 is a block diagram of a preferred embodiment where the masteradjusts its received signal to compensate for phase offset. Thearchitecture of the slave 664 is like that of the slave 310 in theconventional architecture for the telecom model as described withrespect to FIG. 3. The recovered clock signal 617 is synchronized withthe frequency and phase of the clock signal 606. At the master 660, thereceived signal 636 and the clock signal 606 are synchronized infrequency, however the phases are different because of propagationdelay. The phase comparator 602 measures the phase offset, as describedpreviously with respect to FIG. 6. Alternatively, a data comparator canbe used instead of the phase comparator 602, as described previouslywith respect to FIG. 8. The phase adjuster 640 adjusts the receivedsignal 636 to compensate for the phase offset. The phase compensated RXsignal 641 is now synchronized in frequency and phase with the clocksignal 606.

FIG. 13 illustrates examples of signals corresponding to operation ofthe embodiment of FIG. 12. The clock signals 1002, 1006, 1010 and 1014correspond to clock signal 606. The received signals 1004 and 1008correspond to received signal 636 in FIG. 12. The measured phase offsetsof +d or −e are compensated by phase adjustment (− step) or (+ step),respectively. The phase adjuster 640 applies the step adjustments to thereceived signal 636 to form phase compensated RX signal 641,corresponding to signals 1012 and 1016 in FIG. 13. These examples aresimilar to those described with respect to FIG. 10, except that all thephase compensation operations are performed in the master.

FIG. 14 is a block diagram of a master linked with multiple slavedevices corresponding to the embodiment of FIG. 12. The master 1400includes a phase compare and phase adjust module 1404 i for eachreceived signal 1408 i from each slave 1406 i.

FIG. 15 is a block diagram of a preferred embodiment where the masteradjusts its transmit signal to compensate for phase offset in itsreceived signal. The architecture of this embodiment is like thatdescribed with respect to FIG. 12, except for the position of the phaseadjuster 650. The phase adjuster 650 modifies the clock signal 606 by aphase shift in a direction opposite to the phase offset, calculated bythe phase comparator 602, to produce a phase adjusted clock signal 651.In response to the phase adjusted clock signal 651, the transmitter 624produces a transmit signal whose phase is opposite to the measured phaseoffset. Referring to the example illustrated in FIG. 16, the phaseoffset between the clock signal 1002 and the received signal 1004 is +d.The phase adjustment applies a (− step) change in the phase of the clocksignal 606 to produce the phase adjusted clock signal 651. As a result,the transmit signal 1020 has a phase of approximately −d. When thistransmit signal 1020 is received at the slave 664, the CDR module 616locks to the adjusted phase and produces a clock signal 617 with a phaseof approximately −d. Since the timing of the slave's transmitter 626 iscontrolled by the phase adjusted clock signal 617, the slave's transmitsignal also has a phase of approximately −d. This phase is substantiallycancelled by propagation over link 627. When the slave's transmit signalis received by the master 660, the master's received signal 636 is morealigned with the clock signal 606, as shown by the signals 1010 and 1012in FIG. 16.

FIG. 17 is a block diagram of a master linked to multiple slavescorresponding to the embodiment of FIG. 15. The master 1700 includes aphase comparator 1706 i for each received signal 1704 i from each slavedevice 1406 i to measure a corresponding phase offset. Each phaseadjuster 1708 i adjusts the phase of the clock signal 1710 so that eachtransmit signal 1702 i has a phase that is opposite to the correspondingmeasured phase offset.

FIG. 18 is a block diagram of an alternative embodiment for the slavedevice 664 in FIGS. 12 and 15. The slave device 1800 includes a clocksource 1802, so it corresponds to the datacom model. The CDR 1808recovers the frequency and phase of an embedded clock of the receivedsignal to generate a clock signal 1810 that matches the frequency of thetransmit clock of the master device. The controller 1812 controls thetransmit jitter buffer 1806 to form the transmit signal in accordancewith the recovered clock signal 1810 instead of the TX clock signal 1804output by the clock source 1802. This allows the slave 1800 to transmitat the frequency of the master's clock, instead of its own clock 1804.Since the slave's transmit signal is matched in frequency to themaster's clock, the master can perform the phase measurements andadjustments described with respect to FIGS. 12 and 15.

Embodiments of the present invention reduce the complexity of a masterdevice that is interconnected with one or more slave devices byeliminating the PLL in the master device that would be required for eachconnection in conventional architectures. Referring back to FIG. 5showing a block diagram of a PLL, the conventional PLL includes a phasecomparator 500, a loop filter 506 and a controlled oscillator 512.Embodiments of the present invention include a phase comparator, but donot require the loop filter 506 or the controlled oscillator 512 in themaster device. The PLL in the CDR at the slave device provides that theslave's transmit signal is synchronized in frequency with the master'sclock signal. Simpler phase adjustment operations by the master or slaveprovide the phase compensation in the received signal at the masterdevice. Several applications are described in the following.

In an application with an ADC in communication with a digital processor,an embodiment of the present invention implements the operations of themaster in the digital processor. The ADC converts an input analog signalto a digital signal that is transferred to the digital processor. Theslave's operations can be implemented in a digital portion of the ADCdevice or a digital interface for transferring the digital signal fromthe ADC to the digital processor.

The applications for ADC can be used in a digital radio system. Anembodiment of the present invention positions the ADC near the (AFE) ofthe receiver of a digital radio system. The ADC digitizes the receivedanalog signal and transfers it the over a digital link to a digitalprocessor for signal processing and demodulation operations.

In an application where a digital processor is connected with one ormore memory devices, an embodiment of the present invention implementsthe operations of the master in the digital processor and the operationsof the slave in the memory device. The embodiments where the masterperforms the phase adjustment operations, described with respect toFIGS. 12 and 15, are preferable because the simpler architecture of theslave is preferable for the memory device.

Specific implementations of the master and slave devices depend on theapplication and the functions of the interconnected devices.Implementations of master and slave operations can use one or moredigital processing technologies appropriate for the application,including FPGA, complex programmable logic devices (CPLD), ASIC, digitalsignal processor (DSP), microcontroller and microprocessor. For theembodiments of FIGS. 6, 8 and 9, a phase comparator and control symbolencoder can be implemented instead of a PLL in the master device. Forthe embodiments of FIGS. 12 and 15, a phase comparator and phaseadjuster can be implemented instead of a PLL in the master device. Forthe embodiments of FIGS. 6, 7 and 9, implementation of the slaveincludes operations for control symbol decoding and for phasecompensation of the transmit signal. For the embodiment of FIG. 18,implementation of the slave includes operations for phase compensationof the transmit signal. Reducing the requirements for PLLs in the mastersignificantly reduces the complexity of the communications overhead forthe device and frees resources for other aspects of the application.

While the preferred embodiments of the invention have been illustratedand described, it will be clear that the invention is not limited tothese embodiments only. Numerous modifications, changes, variations,substitutions and equivalents will be apparent to those skilled in theart, without departing from the spirit and scope of the invention, asdescribed in the claims.

1. In a system having at least two interconnected devices, wherein afirst device and a second device are connected by a data transfer link,the first device including a clock source and the second deviceincluding a phase lock loop, a method for reducing a phase offset of asignal received at the first device, comprising: at the first device,transmitting a prior signal from the first device to the second devicein accordance with a clock signal from the clock source; at the seconddevice, receiving the prior signal at the second device to form areceived prior signal; applying the phase lock loop to the receivedprior signal to form a recovered clock signal synchronized to thereceived prior signal; generating a first transmit signal in accordancewith the recovered clock signal; transmitting the first transmit signalto the first device; at the first device, receiving the first transmitsignal to form a first received signal; measuring the phase offsetbetween the first received signal and the clock signal to form a firstphase offset; and adjusting the first received signal to reduce thefirst phase offset to form a phase compensated received signal.
 2. Themethod of claim 1, wherein at the first device, the step of measuringthe phase offset further comprises: comparing a signal phase of thefirst received signal to a clock phase of the clock signal to determinethe first phase offset.
 3. The method of claim 1, wherein the firstreceived signal contains a training pattern represented at the firstdevice in a reference training pattern, the step of measuring the phaseoffset further comprising: at the first device, extracting the trainingpattern from the first received signal to form a received trainingpattern; and comparing the received training pattern with the referencetraining pattern to determine the first phase offset.
 4. The method ofclaim 1, further comprising: at the first device, inserting a trainingpattern in the prior signal for the step of transmitting a prior signal,wherein at the second device, the received prior signal contains thetraining pattern, wherein the step of generating a first transmit signalincludes inserting the training pattern in the first transmit signal. 5.The method of claim 1, wherein at the first device, the step ofadjusting the first received signal further comprises: adjusting a clockphase of the clock signal to reduce the first phase offset forming aphase compensated clock signal; and forming the phase compensatedreceived signal in accordance with the phase compensated clock signal.6. The method of claim 1, wherein the second device includes an analogto digital converter, the method further comprising: at the seconddevice, sampling an analog signal using the analog to digital converterto form a plurality of signal samples; and encoding the signal samplesto form the first transmit signal.
 7. The method of claim 1, wherein thefirst device comprises a field programmable gate array performing thesteps of the first device.
 8. The method of claim 1, wherein the seconddevice comprises a field programmable gate array performing the steps ofthe second device.
 9. In a system having at least two interconnecteddevices, wherein a first device and a second device are connected by adata transfer link, an apparatus for reducing a phase offset of a signalreceived at the first device, comprising: at the first device, a clocksource that generates a clock signal; a first transmitter coupled to thedata transfer link and the clock source, the first transmitter forming aprior signal in accordance with the clock signal and transmitting theprior signal over the data transfer link to the second device; at thesecond device, a second receiver coupled to the data transfer link, thesecond receiver receiving the prior signal to form a received priorsignal; a phase lock loop coupled to receive the received prior signal,the phase lock loop generating a recovered clock signal synchronizedwith the received prior signal; a second transmitter responding to therecovered clock signal to form a first transmit signal synchronized withthe recovered clock signal, the second transmitter transmitting thefirst transmit signal over the data transfer link to the first device;at the first device, a first receiver that receives the first transmitsignal to form a first received signal; a phase comparator coupled tothe first receiver and the clock source, the phase comparator measuringthe phase offset between the first received signal and the clock signalto form a first phase offset; and a phase compensator coupled to receivethe first received signal, the first phase offset and the clock signal,the phase compensator adjusting the first received signal to reduce thefirst phase offset to form a phase compensated received signal.
 10. Theapparatus of claim 9, wherein at the first device, the phase comparatorcompares a signal phase of the first received signal to a clock phase ofthe clock signal to determine the first phase offset.
 11. The apparatusof claim 9, wherein the first received signal contains a trainingpattern represented at the first device in a reference training pattern,the phase comparator further comprising: a pattern decoder coupled tothe first receiver and extracting the training pattern from the firstreceived signal to form a received training pattern; and a datacomparator coupled to the pattern decoder and comparing the receivedtraining pattern to the reference training pattern to determine thefirst phase offset.
 12. The apparatus of claim 9, further comprising: atthe first device, a training pattern generator coupled to the firsttransmitter and inserting a training pattern in the prior signal, thefirst transmitter transmitting the prior signal over the data transferlink; and at the second device, a loopback controller coupled to thesecond receiver and the second transmitter, the second receiverreceiving the prior signal to form a received prior signal containingthe training pattern and the second transmitter responding to theloopback controller to transmit the training pattern in a second priorsignal over the data transfer link to the first device, the second priortransmit signal forming the first received signal at the first device.13. The apparatus of claim 9, wherein the phase compensator furthercomprises: a clock phase adjuster coupled to receive the clock signaland the first phase offset, the clock phase adjuster applying a phaseshift to the clock signal to reduce the first phase offset forming aphase compensated clock signal, wherein the phase compensator respondsto the phase compensated clock signal to form the phase compensatedreceived signal.
 14. The apparatus of claim 9, wherein the second devicefurther comprises: an analog to digital converter coupled to receive ananalog signal and producing a plurality of signal samples; and a signalencoder coupled to receive the signal samples from the analog to digitalconverter, the signal encoder encoding the signal samples to form thefirst transmit signal.
 15. The apparatus of claim 9, wherein the firstdevice is implemented in a field programmable gate array.
 16. Theapparatus of claim 9, wherein the second device is implemented in afield programmable gate array.
 17. In a system having a master deviceconnected to a plurality of slave devices by a plurality of datatransfer links, wherein each of a plurality of signals received at themaster device has a corresponding phase offset, an apparatus forreducing each phase offset, comprising: at the master device, a clocksource that generates a clock signal; a plurality of first transmitters,each first transmitter coupled to a corresponding data transfer link andthe clock source, each first transmitter forming a corresponding priorsignal in accordance with the clock signal and transmitting thecorresponding prior signal to a corresponding slave device; at eachslave device, a second receiver coupled to the corresponding datatransfer link, the second receiver receiving the corresponding priorsignal to form a received prior signal; a phase lock loop coupled toreceive the received prior signal, the phase lock loop generating arecovered clock signal synchronized with the received prior signal; asecond transmitter responding to the recovered clock signal to form acorresponding first transmit signal synchronized with the recoveredclock signal, the second transmitter transmitting the correspondingfirst transmit signal over the corresponding data transfer link to themaster device; at the master device, a plurality of first receivers,each first receiver receiving the corresponding first transmit signal toform a corresponding first received signal; a plurality of phasecomparators, each phase comparator coupled to a corresponding firstreceiver and the clock source, each phase comparator measuring the phaseoffset between the corresponding first received signal and the clocksignal to form a corresponding first phase offset; and a plurality ofphase compensators, each phase compensator coupled to receive thecorresponding first received signal and the corresponding first phaseoffset, each phase compensator adjusting the corresponding firstreceived signal to reduce the corresponding first phase offset to form acorresponding phase compensated received signal.